The system stores both connectivity and geometry so that analysis and synthesis tools can easily acquire the information they need. For example, the incremental design-rule checker uses connectivity information to avoid complaining about situations that other locality-based checkers would erroneously flag. These are the tools available in Electric:

Design-Rule Checking

The incremental design-rule checker watches all changes made to the layout and displays error messages when violations are detected. It checks for spacing errors, notch errors, and minimum size violations.

A hierarchical design-rule checker does a thorough check of the circuit but takes longer to run.

Electrical-Rule Checking

The electrical-rule checker examines all well areas, ensuring proper contacts and spacings.

It also is able to check for antenna rules violations.

Simulation

Electric has a built-in 12-state switch-level simulator, called ALS. It also supports a built-in version of the IRSIM simulator. These simulators display waveforms in a separate window and let users cross-probe from either the waveform or the circuit window.

Simulation Interface

Electric is able to produce input decks for a number of popular simulators, including:

• Device-level simulators such as Spice.
• Switch-level simulators such as Silos, Tegas, IRSIM, ESIM, RSIM, RNL, Cosmos, and Mossim.
• Behavioral-level simulators such as Verilog.
• Miscellaneous simulators such as PALs.

Users of Electric must obtain these simulators on their own.

Generation

The CMOS PLA generator works from a library of PLA elements, thus allowing customized arrays.

The ROM generator builds a ROM layout from a personality table.

The Pad Frame generator places pad cells around a chip core and wires them together.

Compaction

The compactor adjusts geometry to its minimal spacing in the X and Y axes.

Logical Effort

Logical Effort is a system for marking digital schematic gates with fanout information that will produce optimally fast circuits.

Routing

The maze router runs single wires between points.

The cell stitching router make explicit connections where cells abut or overlap.

The mimic router watches user activity. When it sees a wire being created or deleted, it repeats the activity in similar situations throughout the circuit.

The river router runs multiple parallel wires in a channel between cells.

VHDL

The VHDL system can generate VHDL from a layout, and can compile VHDL to netlists of various format. These netlists can then be simulated with the built-in simulator, turned into layout with the silicon compiler, or saved to disk for use by external simulators. Electric

Silicon Compiler

The Silicon Compiler places and routes standard cells from a structural netlist (which can be obtained from VHDL which can be obtained from a schematic drawing).

Network Consistency Checking (LVS)

The network consistency checker uses the "Gemini" algorithm to compare a layout with its equivalent schematic. It can also compare two different versions of a layout or two different versions of a schematic.

Project Management

This built-in system allows users to share a library of circuitry. Users can check out cells for editing and check them back in when done. Other users are prevented from changing checked-out cells, and can have their circuits updated when changes are checked in.

In addition, users are prevented from making changes to checked-out cells that would affect other cells that are not checked-out. Also, warnings are issued when multiple users check-out cells that are hierarchically related which may cause interference in their editing.