effects (such as leakage power) that can’t be fixed by libraries and/or tools alone. These must be addressed by architectural tradeoffs. With due diligence on the part of allconcerned, we can keep nanometer effects (barely) under control. Ed Cheng Synopsys, Inc., Mountain View, CASang Wang Nassda Corp., Santa Clara, CAThe top three issues putting the semiconductor industryat risk:1. Prevalent nanometer effects inducing more seriouscircuit timing, power and signal integrity problemswill cause frequent silicon failures. These nanometereffects stemming from interconnect parasitics and nonlinear device behavior are very difficult tocontrol without accurate accounting for their details. 2. Very large circuit size or high circuit complexity(such as mixed analog, digital and memorycomponents) exceeding most simulation and verification tools’ capacity or substantially slowingdown tools’ performance. This significantly reduces designers’ effectiveness in understanding andsolving difficult circuit problems at the whole-chiplevel. 3. A lack of efficient and reliable layout extractorshinders effective post-layout circuit verification andcircuit optimization. Without full-chip detailedsimulations with reasonably accurate extracted layout parameters and parasitics, users have littlecontrol in assuring working silicon and good yield. Which constituency will solve these issues, and how?1. Highly accurate and efficient simulation and analysis tools are needed to thoroughly understandand resolve nanometer effects so that silicon successcan be achieved for Nanometer circuits. 2. Tools must support very large circuit capacity withvery high computational performance to control theever-increasing design size and turnaround timerequirements. Mature mixed-level and hierarchical tools are two possible solutions. 3. Mature extractors are key. Hierarchical extractorswill be most effective but are very difficult to develop. Hierarchical parasitic backannotation is analternative and the solution is around the corner for users to have a control of post-layout full-chip verification.592Proceedings of the 38th Design Automation Conference (DAC’01) 1-58113-297-2/01 $ 10.00 © 2001 ACM