Panel:Is Nanometer Design Under Control?Chair:Andrew B. Kahng, Professor of CSE and ECE, UC San Diego, La Jolla, CAOrganizers: Bing Sheu, Nassda Corp., Santa Clara, CA, and Andrew B. Kahng, UC San Diego, La Jolla, CAAbstractAs fabrication technology moves to 100 nm and below,profound nanometer effects become critical in developing silicon chips with hundreds of millions oftransistors. Both EDA suppliers and system houses havebeen re- tooling, and new methodologies have been emerging. Will these efforts meet the challenges ofnanometer silicon such as performance closure, power,reliability, manufacturability, and cost? Which aspects ofnanometer design are, or are not, under control? Thissession will consist of a debate between two teams ofdistinguished representatives from EDA suppliers and system design houses. Which side has the right answersand roadmap? You and a panel of judges will decide!Nancy Nettleton Sun Microsystems, Palo Alto, CAThe top issues in nanometer design that I believe willplace semiconductor designs at the greatest risk arephysical chip planning/integration and signal integrity.Both issues cross a broad range of design disciplines, design tools, and design project scope. Neither issue isbeing effectively addressed today without significanthomebrew EDA development. Both issues willultimately require systemic changes to the way wedesign chips; not just the way we hook tools together, butthe way we plan projects and organize teams. I expect both issues will most likely be addressed bydesign methodologists, for two reasons:1. Design methodologists have the most momentum onthese issues today.2. Design methodologists have a better vantage pointof the entire design flow from which to make the kind of systemic changes that will be required.John Cohn IBM Microelectronics, Burlington, VTAs we enter the nanometer design space, we findourselves in an ever-tightening box between design closure issues, schedule pressure and increasing technology complexity. While many problems such astiming closure, power management and signal integrity are getting lots of attention, three problems that may notbe getting the attention they deserve are: designpredictability, cost, and methodology integration. Our ability to profitably build big, fast chips is basedentirely on our ability to accurately predict their performance, reliability, and design effort in the face ofan ever-growing list of technology challenges. In thenanometer design era these challenges includes suchtough to modelling issues as device leakage, short channel effects, increased soft error sensitivity, substratenoise and increased parametric variation. In the interestof productivity, commercial tools are addressing thesepredictability problems by over-design and abstraction,in effect moving us away from the technology. The resultis a widening performance gap between ASIC/SoC designs and more custom approaches. Chip cost is another parameter that has seen surprisinglylittle focus from CAD vendors. Just because our methodologies enable us to make complex systems on a single die doesn't mean that it's always economically wise to do so. In fact, many of the things we have donein the interest of productivity actually lead to lowerperformance, larger dies, and thus higher costs. Currenttool approaches tend to obscure the intrinsic trade-offbetween cost, design effort and other design metrics,again moving us away from the technology. The result isan overall poor ability for the industry to optimizeprofitability.A final risk I see in the Nanometer design space relates tothe direction taken by many of the major CAD providers. In response to the deep sub-micron bogeyman, mostCAD providers are attempting to soften the traditionalboundaries between logical and physical design. This has given rise to a very powerful set of ‘blended’ toolsoffering combined synthesis, physical design and analysis. While the benefit is easier and faster designclosure, the result is an overall loss in methodologyflexibility due to the difficulty of mixing and matchingmethodology components from several sources. Combining the concerns about technology predictability and cost with the complexity of large mixed-content SoC designs absolutely argues against any 'one size fits all’ solution. A closed design system, no matter how elegant,will never contain the best of all current approaches. The solutions to these tough problems will not come from asingle CAD company, silicon house or university, butrather from a synthesis of the best evolving knowledgefrom all of the sources. This then begs the question:“Who will best solve the nanomenter design problem ?”The answer is “Those who best understand the rules: the people that build the silicon.!.” 591Proceedings of the 38th Design Automation Conference (DAC’01) 1-58113-297-2/01 $ 10.00 © 2001 ACM
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Shekhar BorkarIntel Corporation, Hillsboro, CAThere are several issues when it comes to nanometerscale technologies. Transistors in this regime could havesevere short channel effects, reducing their effectivenessin high speed circuits and logic. Parameter variationscould affect circuit functionality and yield. And the highspeed circuits that we depend on today to provide performance boost (e.g., domino) will cease to function.Technologists and circuit designers are aware of theseproblems and are working hard to solve them; therefore,these issues pose moderate risk from the technologystandpoint. However, the EDA community is completelyoblivious to this, and is solving today’s mundane problems, extrapolating into the nanometer regime. As a result, we might have process and circuit technology for nanometer scale, but no design technology to takeadvantage of the nanometer technology. This is the major risk moving forward. Louis SchefferCadence Design Systems, Inc., San Jose, CAThe biggest risk to Nanometer design is any effect that: 1. affects many nets and/or cells, so it can’t be fixed byhand;2. cannot be addressed without major changes to tools or libraries, both of which have very long lead times;or3. can’t be fixed by methodology without unacceptable overhead. Three effects come to mind that meet these criteria - leakage currents, soft errors, and manufacturability requirements such as antenna rules. Leakage currents are most easily addressed by architectures that allow power switching and/or new libraries and tools that can takeadvantage of them. Both of these are long lead timeitems, so we need to thinking about leakage now or werisk a crisis later. Soft errors are a similar problem, witha complete library re-design required if the effect isworse than anticipated. Manufacturing rules can have asimilar effect - indeed this almost happened with antennarules during the 0.18 micron to 0.13 micron transition.These rules became much more restrictive and the EDA vendors were barely able to respond in time. A similarunanticipated manufacturing requirementcouldprecipitate a crisis, with no chips produced until asolution is invented. Who is responsible for anticipating these problems?Library creators and vendors will need to step up theirefforts; in-house library creation and/or tight cooperationwill be needed to anticipate any process quirks in timefor early production. Next, the fabs need to be upfrontabout any new manufacturability requirements, and theCAD vendors must take them seriously.Finally designers need to understand those