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4.1SPEED AND CAPACITYTo demonstrate the performance of SignalStorm NDC, four designs were analyzed using the samecomputer hardware: a 32-bit Linux machine with an Intel x86 Xeon chip running at 2.4 GHz, with4 GB of real memory (see Table 1).Table 1: Speed and capacity performance of SignalStorm NDC4.2FAILURE ANALYSIS: EFFECTS OF IR DROPIn this case, delay calculation using SignalStorm NDC determined the cause of a design’s failure in silicon(see Table 2). The initial, traditional delay calculation ignored IR drop, but after the design was analyzedusing SignalStorm NDC to take IR drop into account, the results validated that hold time violations causedthe failure—which the traditional analysis missed. For nanometer designs, instance-based IR dropinformation from VoltageStorm power analyzer can be included in the delay calculation simply by loading adata file into SignalStorm NDC. Table 2: Avoiding silicon failure by analyzing IR dropNote the difference in slack between the traditional (0.111 ns) and SignalStorm NDC (-0.052 ns)approaches, and the close correspondence between SignalStorm NDC and HSPICE.5CONCLUSIONNow that the nanometer era has become a reality, delay calculation will assume an even more importantrole in bringing these designs successfully to market—within a practical time frame and using readilyavailable hardware. A new delay calculator for nanometer designs, SignalStorm NDC operates quickly,boosting speed by up to 5x, and uses computing resources efficiently, consuming up to 80% less memorythan traditional tools. The models in SignalStorm NDC predict silicon behavior accurately to meet theever-growing complexity of the most challenging Nanometer designs.7Validation Standard timing ignoring IR drop SignalStorm NDC + VoltageStorm including IR drop(Times in ns) Data Data Slack Data Data Slack available required available required SignalStorm 3.759 3.648 0.111 3.751 3.803 -0.052Pearl DC + PT STA 3.95 3.83 0.120 Feature not availableHSPICE 3.808 3.66 0.148 3.811 3.83 -0.019Case Input Output Peak memory Total CPU time (minA No-coupling g-zipped Full-chip g-zipped 850 MB 28 (34 real runtime) flat DSPF (1.65 M nets, flat SDF 1.4.1 M instances)B No-coupling g-zipped Full-chip g-zipped 2.1 GB 62 (72 real runtime) flat SPEF (3.12 M nets, flat SDF 3.0 M instances) C Hierarchical IP database Full-chip g-zipped 1.2 GB 17 (18 real runtime) (14 blocks, 2.16 M nets, flat SDF 1.98 M instances) D Hierarchical IP database Full-chip g-zipped 1.0 GB 25 (30 real runtime) (5 blocks, 1.65 M nets, flat SDF 1.41 M instances)
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Cadence Design Systems, Inc.Corporate Headquarters2655 Seely AvenueSan Jose, CA 95134800.746.6223408.943.1234www.cadence.com© 2004 Cadence Design Systems, Inc. All rights reserved. Cadence, theCadence logo, SignalStorm, and VoltageStorm are registered trademarksof Cadence Design Systems, Inc. All others are properties of theirrespective holders.5098 1/04