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3.3.3 A match with design needsNanometer chips tend to have long RC interconnects and multidriven nets, including clock meshes. Thesefeatures add a challenging level of complexity to the factors that influence delay, and a delay calculationtool must be able to evaluate all these elements and account for them. SignalStorm NDC can handle RCnetworks by using time-quantized Ceff to model effective capacitance and ECSM to model current. It alsocan more accurately capture frequency-dependent delays that other tools miss, as shown in Figure 4.Figure 4: Comparison of SPICE accuracy on long RC netsThe traditional linear model cannot emulate the behavior of long RC interconnects, which are criticalto design success. In contrast, ECSM in SignalStorm NDC more closely approximates the SPICE results.3.4IR DROP ANALYSIS REDUCES RISKSWhile IR drop (the drop in instantaneous voltage at the cells) has some impact on lower density designs, at180 nm and below a large percentage of designs may fail on first silicon due to excessive IR drop. At 130 nmand below, the effects of IR drop on timing can be profound. In particular, increased clock skew and signalskew in these chips can cause hold time and setup time violations, respectively. See Figure 5.Figure 5: Relation of IR drop to skew and subsequent timing violationsUnfortunately, traditional delay calculators use inherently inaccurate linear K-factors to predict IR dropeffects, with equally inaccurate results. In comparison, SignalStorm NDC models IR drop as a nonlineareffect (see Figure 6). By drawing on their sets of variable current source values, the new, dynamic modelsin SignalStorm NDC can use change in current at the driving point to build a model with RC meshes andto estimate peak drop from peak current and total resistance, calculating overall drop distribution.5Time(s)Voltage (V)10.80.60.40.200.00E+005.00E-101.00E-091.50E-092.00E-09Traditional linear modelWaveform-dependent CeffSPICEVDD = 1.20 VVDD = 1.10 VCLKVDD = 1.17 V