DELAY CALCULATION MEETS THE NANOMETER ERA 1OVERVIEWNow that nanometer technology for ICs has become a reality





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3.2CAPACITY THROUGH HIERARCHICAL CALCULATIONFor large, complex commercial designs, fully hierarchical delay calculation is the optimal method(see Figure 2). An innovative database structure adds this capability to SignalStorm NDC and not onlymaintains speed and efficiency, but also improves them. Performance up to five times faster than withcurrent databases is possible with this hierarchical approach, which also addresses a major issue fornanometer geometries: memory. A hierarchical database reduces the memory required to about one-fifththat of traditional tools. SignalStorm NDC incorporates a bottom-up approach to analysis to ensure thatany changes in child cells are reflected automatically in the parent components. This hierarchical database improves accuracy and adds capabilities, including the ability to accuratelycompute across-block boundary resistance-capacitance (RC) delays. A hierarchical database eliminatesthe use of abstract models, which often are inaccurate, and eliminates the need to build timing modelextracts. No transfers of related files, which can introduce errors, are required. The database inSignalStorm NDC stores multiple SPEF/DSPF files. Figure 2: Hierarchical delay calculationThe type of database and calculation method that SignalStorm NDC uses improves speed and accuracywhile reducing memory usage.3.3ACCURACY TO HELP SPEED TIMING CLOSURENanometer designs offer unprecedented challenges in ensuring that delay calculation is accurate. Due tothe feature size and design complexity of these chips, a delay calculation tool must account for dynamiceffects on delay. In SignalStorm NDC, models used for calculation include much more realistic currentand capacitance characteristics, rather than unworkable “grouped” or “lumped” loading models.And, SignalStorm NDC can predict and handle slew, one of the toughest timing requirements to meet.3.3.1 A new, time-quantized model of effective capacitance (Ceff) Central to the accuracy of delay calculation is modeling of effective capacitance (Ceff). Traditionally,Ceff models use single values. This approach is only marginally adequate to predict delay (the resultingslew values may end up to be 20% different from the actual values, leading to significant delaycalculation errors). 3DBAChipChipCADCBCC

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    DELAY CALCULATION MEETS THE NANOMETER ERA 1OVERVIEWNow that nanometer technology for ICs has become a reality


    --------------------------------------------------------------------------------
    Page 5
    3.2CAPACITY THROUGH HIERARCHICAL CALCULATIONFor large, complex commercial designs, fully hierarchical delay calculation is the optimal method(see Figure 2). An innovative database structure adds this capability to SignalStorm NDC and not onlymaintains speed and efficiency, but also improves them. Performance up to five times faster than withcurrent databases is possible with this hierarchical approach, which also addresses a major issue fornanometer geometries: memory. A hierarchical database reduces the memory required to about one-fifththat of traditional tools. SignalStorm NDC incorporates a bottom-up approach to analysis to ensure thatany changes in child cells are reflected automatically in the parent components. This hierarchical database improves accuracy and adds capabilities, including the ability to accuratelycompute across-block boundary resistance-capacitance (RC) delays. A hierarchical database eliminatesthe use of abstract models, which often are inaccurate, and eliminates the need to build timing modelextracts. No transfers of related files, which can introduce errors, are required. The database inSignalStorm NDC stores multiple SPEF/DSPF files. Figure 2: Hierarchical delay calculationThe type of database and calculation method that SignalStorm NDC uses improves speed and accuracywhile reducing memory usage.3.3ACCURACY TO HELP SPEED TIMING CLOSURENanometer designs offer unprecedented challenges in ensuring that delay calculation is accurate. Due tothe feature size and design complexity of these chips, a delay calculation tool must account for dynamiceffects on delay. In SignalStorm NDC, models used for calculation include much more realistic currentand capacitance characteristics, rather than unworkable “grouped” or “lumped” loading models.And, SignalStorm NDC can predict and handle slew, one of the toughest timing requirements to meet.3.3.1 A new, time-quantized model of effective capacitance (Ceff) Central to the accuracy of delay calculation is modeling of effective capacitance (Ceff). Traditionally,Ceff models use single values. This approach is only marginally adequate to predict delay (the resultingslew values may end up to be 20% different from the actual values, leading to significant delaycalculation errors). 3DBAChipChipCADCBCC