TECHNICAL PAPERDELAY CALCULATION MEETS THE Nanometer ERA
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TABLE OF CONTENTS1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Why a new solution is needed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Capabilities of a Nanometer delay calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Real-world successes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7FIGURES AND TABLESFigure 1The impact of accuracy on timing closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Figure 2Hierarchical delay calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 3Variable current source modeling with ECSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Figure 4Comparison of SPICE accuracy on long RC nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 5Relation of IR drop to skew and subsequent timing violations . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 6Comparison of delay results from K-factor and nonlinear models . . . . . . . . . . . . . . . . . . . . . . . 6Figure 7SignalStorm NDC interaction with other tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Table 1Speed and capacity performance of SignalStorm NDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 2Avoiding silicon failure by analyzing IR drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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1OVERVIEWNow that nanometer technology for ICs has become a reality, identifying and analyzing interconnectdelays has assumed a higher profile than ever. As process geometries get smaller, interconnect delaymakes up the majority of total delay and greatly affects the outcome of nanometer designs. Today’sdenser ICs show increased sensitivity to variations in power supply, which means that prediction of IR(voltage) drop and ground bounce is now essential for delay calculation.Unfortunately, traditional delay calculation methods fall short in many areas for use with nanometerdesigns—just at the time when delay calculation has become more critical. Today’s tools needimprovement in their predictive capabilities, which calls for more sophisticated modeling, databases,and related technologies. At the same time, delay calculation tools must maintain—or ideally improve—their speed and capacity to make them practical for designers. By using these tools near the end of thedesign cycle, designers can have a powerful aid in mitigating the risk of design failure, as long as theanalyses are accurate.Fortunately, new approaches in delay calculation are becoming available to help design teams minimizesilicon re-spins, shorten design cycles, ensure chip performance, and maintain high yields. One of the mostinnovative of these tools is the Cadence®SignalStorm®NDC (nanometer delay calculator). SignalStormNDC excels at performing delay calculation of designs with 10 M gates or more, accurately handlingmultidriven nets and meshes. SignalStorm NDC:• Runs two to five times faster and uses 80% less memory than traditional tools. • Offers new methods for calculation and modeling of effective capacitance and current source. • Accurately models the nonlinear impact of IR drop on delay.This paper discusses the consequences of staying with outdated methods and why a new generationof delay calculation tools such as SignalStorm NDC is needed. The paper also explores in detail thenew requirements for the nanometer era and presents some case studies. 2WHY A NEW SOLUTION IS NEEDEDAs designs become more dense and approach the 90 nm range, present delay calculation tools—bothwithin and independent from static timing analyzers (STAs)—are reaching their performance limits foruse with these geometries. Today’s designs have become so complex that traditional methods may nolonger provide acceptable performance. These designs seriously challenge a tool’s speed and capacity,so that the analysis process becomes drawn out. The latest high-performance chip designs may contain blocks that use multilevel design methodologies,which allows greater variation in voltage due to tighter control of power supply values. For successful delaycalculation on these designs, tools must have models that account for the sources of variation in nonlinearsignals and power supply voltage changes—which traditional models do not. In addition, modeling of inputpin capacitance presently is inadequate because it is based on fixed values instead of dynamic values, whichcan lead to up to 30% inaccuracy in delay calculation for nanometer designs. And, the use of multiplelibraries generates enormous amounts of data, making analysis and debugging difficult.Traditional tools also lack effective models that account for the dynamic current and capacitancecharacteristics required for accurate assessments of nanometer designs. These calculators cannotaccurately model the conditions involved in wire loading and IR drop, for example. The modelsused now are too crude and cannot handle the nonlinear character of current and IR drop behavior.2.1REAL-WORLD CONSEQUENCESOverlooking inadequate delay calculation has real consequences for the design process. Inaccurateanalysis results can create a false sense of optimism, leading to missed problems and ultimately todesign failures. Conversely, inaccurate results can promote overly conservative designs that do not takeadvantage of the Nanometer process, leading to a lack of competitiveness in the marketplace. Thesescenarios result from false negative and false positive information from the delay calculation tools.1